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Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 22 differential LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Output skew: 100ps (maximum) * Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Additive phase jitter, RMS: 0.04ps (typical) * 3.3V supply mode * 0C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer and a member HiPerClockSTM of the HiPerClockSTMFamily of High Performance Clock Solutions from ICS. The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8534-01's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
ICS
BLOCK DIAGRAM
CLK_SEL CLK nCLK PCLK nPCLK
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCCO nQ13 Q13 nQ12 Q12 nQ11 Q11 nQ10 Q10 nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO
0
22 22
Q0:Q21 nQ0:nQ21
1
LE Q OE D
VCCO nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 VCCO
ICS8534-01
VCCO Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VCCO
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VCCO nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE OE nc nc nQ21 Q21 VCCO
64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View
REV. A NOVEMBER 19, 2004
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Power Unused Power Input Input Input Input Input Power Input Output Output Output Output Output Description Output supply pins. No connect. Core supply pin. Pulldown Non-inver ting differential clock input pair. Pullup/ Inver ting differential clock input pair. Pulled to 2/3 VCC. Pulldown Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pullup When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input pair. Pullup/ Inver ting differential LVPECL clock input pair. Pulled to 2/3 VCC. Pulldown Power supply ground. Output enable. When logic HIGH, the outputs are enabled (default). Pullup When logic LOW, the outputs are disabled and drive differential low: Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 16, 17, 32, 33, 48, 49, 64 2, 3, 12, 13 4 5 6 7 8 9 10 11 14, 15 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 50, 51 52, 53 54, 55 56, 57 58, 59 60, 61 62, 63 NOTE: Pullup and Name VCCO nc VCC CLK nCLK CLK_SEL PCLK nPCLK V EE OE nQ21, Q21 nQ20, Q20 nQ19, Q19 nQ18, Q18 nQ17, Q17 nQ16, Q16 nQ15, Q15 nQ14, Q14 nQ13, Q13 nQ12, Q12 nQ11, Q11 nQ10, Q10 nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Pulldown refer
Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Output Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. Output Differential clock outputs. LVPECL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. A NOVEMBER 19, 2004
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions Minimum Typical 4 37 75 Maximum Units pF K K
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 0 1 1 CLK_SEL 0 1 0
1
Q0:Q21 LOW LOW CLK PCLK
Outputs nQ0:nQ21 HIGH HIGH nCLK nPCLK
Disabled
nCLK, nPCLK CLK, PCLK
Enabled
OE
nQ0:nQ21 Q0:Q21
FIGURE 1. OE TIMING DIAGRAM
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REV. A NOVEMBER 19, 2004
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 22.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA=0C TO 85C
Symbol VCC VCCO I EE Parameter Core Supply Voltage Ouptut Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 230 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA=0C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE, CLK_SEL OE, CLK_SEL -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA=0C TO 85C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
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REV. A NOVEMBER 19, 2004
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCC - 1.4 VCC - 2.0 1 VCC VCC - 0.9 VCC -1.7 1.0 Minimum Typical Maximum 150 5 Units A A A A V V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA=0C TO 85C
Symbol IIH IIL VPP VCMR VOH VOL Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA=0C TO 85C
Symbol fMAX t PD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section; NOTE 4 Output Rise/Fall Time Setup Time Hold Time Output Duty Cycle f 266MHz f 500MHz 2.0 Test Conditions Minimum Typical Maximum 500 3.0 100 700 (12KHz to 20MHz) 20% to 80% 200 1.0 0.5 48 52 54 0.04 700 Units MHz ns ps ps ps ps ns ns % %
tsk(o) tsk(pp) tjit
tR / tF tS tH odc
266 < f 500MHz 46 All parameters measured at fMAX unless noted otherwise. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 156.25MHz (12KHz - 20MHz) = 0.04ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC
LVPECL
nQx
V EE
nCLK, nPCLK
V
PP
Cross Points
V
CMR
CLK, PCLK
-1.3V 0.165V
V EE
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART 1 nQx Qx PART 2 nQy Qy
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy nQy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK, nPCLK
80% Clock Outputs
80% VSW I N G
CLK, PCLK nQ0:nQ21 Q0:Q21
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nQ0:nQ21 Q0:Q21
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
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FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A NOVEMBER 19, 2004
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
3.3V
3.3V 3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 5F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
tacted through solder as shown in Figure 6. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD
THERMAL RELEASE PATH
The exposed metal pad provides heat transfer from the device to the P.C. board. The exposed metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is conSOLDER M ASK
SIGNAL TRACE
SOLDER
SIGNAL TRACE
GROUND PLANE
THERM AL VIA
Expose Metal Pad (GROUND PAD)
FIGURE 6. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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REV. A NOVEMBER 19, 2004
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8534-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8534-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 230mA = 796.95mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 22 * 30mW = 660mW
Total Power_MAX (3.465V, with all outputs switching) = 797mW + 660mW = 1457mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.457W * 17.2C/W = 110.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
64-PIN TQFP, E-PAD, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
200
17.2C/W
500
15.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
200
17.2C/W
500
15.1C/W
TRANSISTOR COUNT
The transistor count for ICS8534-01 is: 1474
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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
64 LEAD TQFP, E-PAD
PACKAGE OUTLINE - Y SUFFIX
FOR
-HD VERSION HEAT SLUG DOWN
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc D3 & E3
8534AY-01
ACD-HD MINIMUM NOMINAL 64 -0.05 0.95 0.17 0.09 -0.10 1.0 0.22 -12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC 0.45 0 -2.0 0.60 ---0.75 7 0.08 10.0
REV. A NOVEMBER 19, 2004
MAXIMUM
1.20 0.15 1.05 0.27 0.20
Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html
15
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Package 64 lead TQFP, E-Pad 64 lead TQFP, E-Pad on Tape and Reel Count 160 per tray 500 Temperature 0C to 85C 0C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8534AY-01 ICS8534AY-01T Marking ICS8534AY-01 ICS8534AY-01
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8534AY-01
www.icst.com/products/hiperclocks.html
16
REV. A NOVEMBER 19, 2004
Integrated Circuit Systems, Inc.
ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Updated Package Outline and Package Dimensions. Date 11/19/04
Rev A
Table
Page 15
8534AY-01
www.icst.com/products/hiperclocks.html
17
REV. A NOVEMBER 19, 2004

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